A study of TOC Buffer management application in semiconductor assembly order management

• Main Authors: Chen, Shih-Yueh, 陳世岳
• Other Authors: Li, Rong-Kwei
• Format: Others
• Language: zh-TW
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/24546351285674697570

碩士 === 國立交通大學 === 管理學院工業工程與管理學程 === 99 === IC design house is a special part of semiconductor industry. Most of IC design house don’t involve in manufacturing, they finish their products via outsourcing. Because of this outsourcing characteristics, supply chain and order management become very important to design houses. We take advantage of S-DBR (Simplified Drum-Buffer-Rope) and CCPM (Critical Chain Project Management) methods of TOC (Theory of Constraint) in this study to improve DDP (Due Date Performance) of assembly order. Trough literature review and case study, we introduce new method to assembly order management (touch-time is more than 20% of lead-time) to response potential delay quickly and sensitively. We also replace the checking point feedback by real-time WIP report to get the latest status of assembly orders. By use of the real-time WIP report and buffer consumption setup, we can provide a clear action suggestion (ex. Expediting, Monitor, Ignore) to order manager to enhance the DDP. After the adoption of new method, the DDP raise up from 65.3% to 90.7% significantly. This conclusion also proves the new buffer management method is beneficial in High touch-time environment (such as semiconductor assembly).