Thermal-Driven Floorplanning for 3D ICs Using Fusion of Thermal-TSV Area
碩士 === 國立中央大學 === 電機工程研究所 === 99 === As the process technology advances, the device size of integrated circuits continues to shrink into the nanometer scale. However, the device size is nearing its physical limits. Besides, interconnect delays are also growing, incurring the bottleneck of chip perfo...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/54961220745682496586 |