| Summary: | 博士 === 國立清華大學 === 材料科學工程學系 === 99 === The wafer-level isothermal electromigration (ISO-EM) test is performed at high current density that is approximately several hundred folds of the normal current density in use. The ISO-EM stress time is very short, around several tens minutes. The ISO-EM test is very low-cost process in industry. The objectives of the dissertation are to investigate (1) the detection of manufacture defects and (2) the lifetime prediction of metal interconnect of the wafer level ISO-EM test.
The detection of manufacture metal defects and the EM lifetime prediction of metal interconnect are proposed in this dissertation. The manufacture metal defects and EM failure modes can be detected by the resistance change ratio with stress time curves in wafer level ISO-EM test. The relationship between resistance change ratio and stress time has been divided into 3 phases (I, II and III) in the wafer ISO-EM test.
The failure modes of the phase I is correlated to the manufacture metal defects. The resistance change ratio of 1% is set to detect the manufacture defects in the manufacture FAB. The abnormal metal process in FAB can be detected on phase I. The failure modes of phase II are typical EM failure modes, indicating that EM occurs on phase II. The resistance change rate of 1.2% is set to predict EM lifetime. The lifetime derived from the wafer level ISO-EM test is about three times longer than that from the package level EM test. Melting at both the metal line and the diffusion barrier layer occur on phase III, which is due to local temperature higher than 2930oC (melting point of TiN) at high current density during stress. The wafer level ISO-EM test is the fast EM test process, which can be used to monitor the manufacture defects and to predict the EM lifetime. The lifetime prediction of the wafer level ISO-EM is fast and low cost compared to the package level EM test.
The concept of internal heating element can be also applied to create isothermal environment around the negative bias temperature instability (NBTI) and EM test structures for both NBTI and EM tests. The internal heating element can raise rapidly the test device structure to elevated temperature. No external heating source, such as a thermal chuck or an oven, is needed. It is a quick wafer level reliability test and can be used in in-line monitoring and screening the devices. In the wafer level EM test, poly-silicon or tungsten in various shapes can be also embedded underneath the regular metal test lines in the wafer. The poly-silicon or tungsten in various shapes act as an internal heating element, i. e. internal furnace. In this design, both current density and temperature can be controlled independently during EM stressing. No package assembly is required in the wafer level EM with embedded structure. It is useful as in-line defect monitoring and life time prediction in the manufacture fabrication process at the wafer level.
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