Design of Interleaving Non-Linear Control Power Factor Correction
碩士 === 國立臺北大學 === 電機工程研究所 === 99 === A power factor correction chip widely used in front-end stage of a power supply system is designed and implemented in the thesis. The power stage uses interleaved boost structure to provide high power factor and to enhance the power density. Moreover, it has a lo...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/29338718774482226965 |
| Summary: | 碩士 === 國立臺北大學 === 電機工程研究所 === 99 === A power factor correction chip widely used in front-end stage of a power supply system is designed and implemented in the thesis. The power stage uses interleaved boost structure to provide high power factor and to enhance the power density. Moreover, it has a lower input ripple current and shrinks the total volume. Meanwhile the nonlinear solution applied in this chip only needs a current feedback loop and an output voltage sampled loop for modulation purposes. Conventional PFC scheme uses a multiplier that is susceptible to linearity problems can be improved by using an integrator. With an integrator, the duty cycle of pwm signal can be controlled precisely that leads to the total harmonic distortion improvement. The chip solely works with uni-polar supply voltage. It also adopts the leading edge blanking circuit and the over current protection circuit to have a better performance. This chip is fabricated with TSMC 0.35um 2P4M CMOS process.
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