Low Cost Design of Optional Key AES Chip
碩士 === 國立臺灣科技大學 === 電子工程系 === 99 === In the thesis, we propose an area-saving universal VLSI architecture for AES encryption/decryption algorithm. To be used as a universal AES encryption/ decryption system and be able to accept a key with three different lengths, 128, 192, and 256 bits, the data-pa...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/3f9hw4 |