Spatio-Temporally-Shared Recongurable Fast Fourier Transform Architecture Design
碩士 === 國立中正大學 === 資訊工程研究所 === 101 === In recent years, the fast Fourier transform (FFT) has become one of the most widely-used computation kernels in many modern systems, such as for communication, image processing, and digital signal processing applications. These wired/wireless communication appli...
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ndltd-TW-100CCU003920962015-10-13T22:23:53Z http://ndltd.ncl.edu.tw/handle/88058293032899318354 Spatio-Temporally-Shared Recongurable Fast Fourier Transform Architecture Design 空間 - 時間共享的可組態式快速傅立葉轉換架構設計 Jun-Yang Peng 彭竣陽 碩士 國立中正大學 資訊工程研究所 101 In recent years, the fast Fourier transform (FFT) has become one of the most widely-used computation kernels in many modern systems, such as for communication, image processing, and digital signal processing applications. These wired/wireless communication applications demand high-performance, flexibility, and scalability. The reconfigurable architectures make excellent tradeoff between flexibility, implementation complexity, and energy efficiency. The traditional FFT structure can be classified into two categories: pipeline-based and memory-based architectures. The former has the strengths of higher throughput and easier controller design, but the hardware area is larger. The latter has the opposite strengths and weaknesses. Leveraging on the partial dynamic reconfiguration technology for flexibility and scalability and on the integration of pipeline-based and memory-based architectures, we propose a novel scalable FFT architecture called Spatio-Temporally-shared Reconfigurable Fast Fourier Transform (STARFFT) architecture. STARFFT can support the simultaneous computation of multiple FFTs of varying sizes from 64 to 8192 points, covering most frequently used modern computing standards. It supports multiple pipelines based on the radix-2 hardware computation blocks that are time-multiplexed among multiple applications such that significant savings in hardware resources are achieved. Both spatial and temporal constraints of applications are all satisfied by STARFFT through resource allocation. Specifically, we propose two algorithms to improve the resource utilization and our experiments show that the algorithms can reduce resources by nearly 50\%. Besides, the results show that reductions in power consumption can reach about 60\% when compared with traditional pipelined-based FFT in multiple applications. Pao-Ann Hsiung 熊博安 2013 學位論文 ; thesis 70 en_US |
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碩士 === 國立中正大學 === 資訊工程研究所 === 101 === In recent years, the fast Fourier transform (FFT) has become one of the most widely-used computation kernels in many modern systems, such as for communication, image processing, and digital signal processing applications. These wired/wireless communication applications demand high-performance, flexibility, and scalability. The reconfigurable architectures make excellent tradeoff between flexibility, implementation complexity, and energy efficiency. The traditional FFT structure can be classified into two categories: pipeline-based and memory-based architectures. The former has the strengths of higher throughput and easier controller design, but the hardware area is larger. The latter has the opposite strengths and weaknesses.
Leveraging on the partial dynamic reconfiguration technology for flexibility and scalability and on the integration of pipeline-based and memory-based architectures, we propose a novel scalable FFT architecture called Spatio-Temporally-shared Reconfigurable Fast Fourier Transform (STARFFT) architecture. STARFFT can support the simultaneous computation of multiple FFTs of varying sizes from 64 to
8192 points, covering most frequently used modern computing standards. It supports multiple pipelines based on the radix-2 hardware computation blocks that are time-multiplexed among multiple applications such that significant savings in hardware resources are achieved. Both spatial and temporal constraints of applications are all satisfied by STARFFT through resource allocation. Specifically, we propose two algorithms to improve the resource utilization and our experiments show that the algorithms can reduce resources by nearly 50\%. Besides, the results show that reductions in power consumption can reach about 60\% when compared with traditional pipelined-based FFT in multiple applications.
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Pao-Ann Hsiung |
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Pao-Ann Hsiung Jun-Yang Peng 彭竣陽 |
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Jun-Yang Peng 彭竣陽 |
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Jun-Yang Peng 彭竣陽 Spatio-Temporally-Shared Recongurable Fast Fourier Transform Architecture Design |
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Jun-Yang Peng |
title |
Spatio-Temporally-Shared Recongurable Fast Fourier Transform Architecture Design |
title_short |
Spatio-Temporally-Shared Recongurable Fast Fourier Transform Architecture Design |
title_full |
Spatio-Temporally-Shared Recongurable Fast Fourier Transform Architecture Design |
title_fullStr |
Spatio-Temporally-Shared Recongurable Fast Fourier Transform Architecture Design |
title_full_unstemmed |
Spatio-Temporally-Shared Recongurable Fast Fourier Transform Architecture Design |
title_sort |
spatio-temporally-shared recongurable fast fourier transform architecture design |
publishDate |
2013 |
url |
http://ndltd.ncl.edu.tw/handle/88058293032899318354 |
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