Study of Slow-Cell Related Issues in ULV SRAM

• Main Authors: Wei-Chung Cheng, 鄭惟中
• Other Authors: Jinn-Shyan Wang
• Format: Others
• Language: zh-TW
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/31341480388481619387

碩士 === 國立中正大學 === 電機工程研究所 === 101 === Embedded SRAM plays an important role in SoC system. To achieve low power operation, develops of UVL SRAM are necessary. Owing to the increasing of process variation in advanced CMOS technologies, the stability and reliability of memory cell are being threatened. The access failure is the most serious in SRAM failure of the past literatures, which are based on 6T bitcell design, and lack of real chips measurement results of the past papers. In order to adapt for the advanced CMOS technologies and ULV design, an access delay slow cell model based on footless 8T is presented in this thesis. A 128x4096 65nm LP SRAM macro was designed for verifying the stackability of locations, voltage heritability, and temporality of the slow cell in the real chips. Finally, according to the characteristics of the slow cell from measurement results, the local word-line boost technique is used to improve the slow cell and a cache design with the slow cell-tolerant is proposed.