| Summary: | 碩士 === 中原大學 === 電子工程研究所 === 101 === In modern VLSI designs, the minimization of power consumption is a very important issue. To minimize power consumption, the use of multiple voltages is a useful approach. However, in a multi-voltage design, the clock skew
control becomes very complicated. Previous works use the delay compensation method to achieve always zero skew among different voltage modes. As a result, a large amount of compensated delay is often required. Based on that observation, in this paper, we try to utilize useful skew among blocks to reduce the amount of compensated delay. We propose a linear programming (LP) approach to formally draw up this problem. Compared with the previous work, experimental results show that our approach can reduce 19.08% compensated delay.
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