| Summary: | 碩士 === 國立交通大學 === 光電工程研究所 === 101 === In this thesis, low temperature and stackable thin film transistors was presented by using novel fabrication approach. Amorphous silicon(a-Si) films was first deposited at 500℃by inductively coupled plasma chemical vapor deposition system(ICPCVD) as the BOX(buried oxide) layer. After that, the a-Si films was transformed to poly-silicon films by using nanosecond laser spike annealing. Thereafter, the crystallinity of the poly-silicon films were examined by X-Ray diffraction(XRD) and transmission electron microscope (TEM) and the grain size was found to be about 300nm. In addition, we have successfully developed high-quality ultra-thin silicon oxide and silicon nitride films through modulation of nitrous oxide, argon flow, RF power and chamber pressure, etc. The leakage current of dielectric thicknesses of both 5nm silicon nitride and 7nm silicon oxide at 6 million volts / cm electric field are less than 10-7 A / cm2
Combining the thermal budget technologies and metal gate, We have fabricated a high performance TFT that exhibits electron mobility of 55 cm2/V-s , low subthreshold swing of 0.3 V/Decade, and high on/off ratio of 105. That stacked transistors are suitable for the integration of three-dimensional integrated circuits (3D-ICs)
Planar back metal gate was fabricated under the channel of TFT and we can adjust threshold voltage at about 0.9V by applying a back-gate bias from-1V to 1V. Therefore, Vth is controllable for different types of logic circuits.
On the basis of low thermal budget technologies transistor, we introduce a multi-layer of oxide/nitride /oxide as MONOS nonvolatile memory (MONOS NVM). Under 16V pulse bias, this MONOS exhibits a fast program/erase speed of 100 ns and 10μs and the memory window is 1V and 1.5V. As a result, the TFT and NVMs with metal-gate fabricated by low thermal budget technologies are promising devices for the hetero-integration in 3D-ICs application.
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