Testing Strategies for Retention Flip-flops

• Main Authors: Hsu, Hao-Wen, 徐浩文
• Other Authors: Chao, Chia-Tso
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/75314384653527203107

碩士 === 國立交通大學 === 電子研究所 === 101 === This thesis presents several issues about testing for retention flip-flops and proposes the corresponding solutions to those issues. A novel test procedure is proposed for detect many defects of retention flip-flops. Furthermore, a specialized ATPG framework is proposed to generate the test vectors for creating as many effective transitions on interconnects in the circuit as possible. The experimental results based on large ISCAS benchmark circuits demonstrate the efficiency of testing retention flip-flops and the advantages of using our proposed ATPG framework.