A High Speed Low Power Pipelined-SAR Analog to Digital Converter Design
碩士 === 國立中山大學 === 資訊工程學系研究所 === 101 === A high speed and low power Pipelined-SAR ADC is proposed in this thesis. The Flash ADC which is often found in traditional Pipelined ADC is replaced by the energy efficient SAR ADC. By taking the advantages of the pipelined ADC with high speed and high resolut...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/06564569866455010495 |