Design of Clock and Data Recovery Circuits with Digital Frequency Calibration Mechanism and Quantization-Noise Shifting Technique
碩士 === 國立臺灣大學 === 電子工程學研究所 === 101 === A clock and data recovery circuit plays an important role in wireline communication system. It removes the jitter and noise of received data caused by long-distance transmission. There are many choices for the implementation architectures, such as phase-locked...
| Main Authors: | , |
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| Format: | Others |
| Language: | en_US |
| Published: |
2013
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| Online Access: | http://ndltd.ncl.edu.tw/handle/07844320880411958852 |