Simultaneous Layer Assignment and Thermal Via Planning for Minimizing The Temperature Rise of Three-Dimensional Integrated Circuits
碩士 === 中原大學 === 電子工程研究所 === 102 === Because of the reduction of wire length, the technology of three-dimensional integrated circuit can be used to improve the circuit speed and reduce the power dissipation. However, due to low thermal conductivities of dielectrics between active layers, the heat gen...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/4qsasn |