A Throughput Driven High Level Synthesis Algorithm to Synthesize Circuits with Multiple Sampling Rates
碩士 === 國立成功大學 === 電機工程學系 === 102 === Current High-level synthesis (HLS) algorithms mainly synthesize components with single sampling rate in a single clock domain. In this work we present a novel throughput driven HLS algorithm that can synthesize a complex hardware block with multiple sampling rate...
Main Authors: | Chung-ChiaHsu, 許峻嘉 |
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Other Authors: | Kuen-Jong Lee |
Format: | Others |
Language: | en_US |
Published: |
2014
|
Online Access: | http://ndltd.ncl.edu.tw/handle/th83r9 |
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