| Summary: | 碩士 === 國立成功大學 === 電機工程學系 === 102 === Due to the increasing complexity of designs, it spends more and more time in routing in the physical design flow. Compared to analog circuits, size of digital circuits in full-custom design is larger, which requires more effort in placement and routing. Thus, this thesis focuses on the routing problem in full-custom digital circuits. We adopt the grid-based routing model to route nets because it is simple and easy to handle DRC rules. Similar to NTHU-Route 2.0, our routing algorithm is composed of four stages. In the initial stage, we project a multilayer design on to a 2D plane, and then perform 2D routing followed by the layer assignment. In the main stage, the solution is improved by using the rip-up and reroute method. This stage adopts 3D multi-source multi-sink maze routing with the history base cost function to route nets. The refinement stage focuses on finding a short-free path for every short net by using different cost function. Finally, some segments are shifted to attach the pins in layout for resolving the DRC violations in the legalization stage. Our detailed router was implemented in the C++ programming language and the routing result was displayed on Laker3®. Experimental results shows our routing method can pass LVS check and minimize the number of DRC violations.
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