Design and Implementation of W-Band Marchand Balun in 0.18 μm CMOS Technology
碩士 === 國立暨南國際大學 === 光電科技碩士學位學程在職專班 === 102 === Abstract We use TSMC 0.18 μ m CMOS process technology to achieve CMOS RFICs W-band RF front-end design and passive component measurement Barron's. Marchand balun using balanced - unbalanced converter, thereby architecture with output matching netwo...
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ndltd-TW-102NCNU16140042019-05-15T21:12:41Z http://ndltd.ncl.edu.tw/handle/y5ws6n Design and Implementation of W-Band Marchand Balun in 0.18 μm CMOS Technology 以0.18微米CMOS技術設計及實現之W頻帶巴倫單端至差動轉換器 FENG-CHENG LIU 劉峯誠 碩士 國立暨南國際大學 光電科技碩士學位學程在職專班 102 Abstract We use TSMC 0.18 μ m CMOS process technology to achieve CMOS RFICs W-band RF front-end design and passive component measurement Barron's. Marchand balun using balanced - unbalanced converter, thereby architecture with output matching networks, to increase the coupling circuit to achieve the required amount of phase difference between the use of multi-layered structure of the chip design. Measurement results need not be in amplitude balance must be less than ± 1.5 dB, phase imbalance must be less than ± 10 ∘ all transmission traces were simulated using Sonnet, conducted jointly by the Agilent ADS simulation, be sure to be consistent with the requirements layout simulation. Measurement frequency is 77 ~ 81GHz, and the total chip area of 0.55 mm2 control within. The simulation results meet the design requirements and achieve Marchand balun through Chip Implementation Center (CIC), followed by to perform high-frequency measurements 110GHz element S-parameter measurement system through the National Nano Device Laboratories(NDL), measurements performed with the design simulation design and implementation of practical operation. Yo-Sheng Lin 林佑昇 2014 學位論文 ; thesis 46 zh-TW |
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碩士 === 國立暨南國際大學 === 光電科技碩士學位學程在職專班 === 102 === Abstract
We use TSMC 0.18 μ m CMOS process technology to achieve CMOS RFICs W-band RF front-end design and passive component measurement Barron's. Marchand balun using balanced - unbalanced converter, thereby architecture with output matching networks, to increase the coupling circuit to achieve the required amount of phase difference between the use of multi-layered structure of the chip design.
Measurement results need not be in amplitude balance must be less than ± 1.5 dB, phase imbalance must be less than ± 10 ∘ all transmission traces were simulated using Sonnet, conducted jointly by the Agilent ADS simulation, be sure to be consistent with the requirements layout simulation. Measurement frequency is 77 ~ 81GHz, and the total chip area of 0.55 mm2 control within.
The simulation results meet the design requirements and achieve Marchand balun through Chip Implementation Center (CIC), followed by to perform high-frequency measurements 110GHz element S-parameter measurement system through the
National Nano Device Laboratories(NDL), measurements performed with the design simulation design and implementation of practical operation.
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Yo-Sheng Lin |
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Yo-Sheng Lin FENG-CHENG LIU 劉峯誠 |
author |
FENG-CHENG LIU 劉峯誠 |
spellingShingle |
FENG-CHENG LIU 劉峯誠 Design and Implementation of W-Band Marchand Balun in 0.18 μm CMOS Technology |
author_sort |
FENG-CHENG LIU |
title |
Design and Implementation of W-Band Marchand Balun in 0.18 μm CMOS Technology |
title_short |
Design and Implementation of W-Band Marchand Balun in 0.18 μm CMOS Technology |
title_full |
Design and Implementation of W-Band Marchand Balun in 0.18 μm CMOS Technology |
title_fullStr |
Design and Implementation of W-Band Marchand Balun in 0.18 μm CMOS Technology |
title_full_unstemmed |
Design and Implementation of W-Band Marchand Balun in 0.18 μm CMOS Technology |
title_sort |
design and implementation of w-band marchand balun in 0.18 μm cmos technology |
publishDate |
2014 |
url |
http://ndltd.ncl.edu.tw/handle/y5ws6n |
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