40nm Low Vmin 256-Kb 8T SRAM Design

• Main Authors: Chang, Zhi-Hao, 張智皓
• Other Authors: Chuang, Ching-Te
• Format: Others
• Language: en_US
• Published: 2013
• Online Access: http://ndltd.ncl.edu.tw/handle/94178994449401691087

碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 102 === In recent years, many novel alternative memory devices have been proposed and researched. Because better access speed of Static Random Access Memory (SRAM), SRAMs are widely used as cache memory in high performance processor and embedded system. Because of the advantages of simple structure, high operation speed and high capacity density, the conventional 6T SRAM is the most widely used in recent years. As environmental protection consciousness, the green power becomes an increasingly important issue in todays. Low-Power and Low-Voltage circuit design becomes a major trend in SoCs recently (System-On-Chip) in todays. However, conventional 6T SRAM is hardly used to operate in low voltage. Thus, several low voltage SRAM cells are proposed. The disturb-free 8T cell is viewed as appropriate choice for low voltage application. The 8T bit-cell occupies lightly addition area and decreases the operation speed relative to conventional 6T cell. This thesis presents a novel two-port disturb-free 8T SRAM cell with cell Vtrip tracing write assist (CVTWA) and cross-point write word line boosting to improve the write-ability. For low power application, we propose the low-swing GRBL technique. To improve performance, we also apply the ripple BL structure to enhance operation speed of test chip. The proposed 8T SRAM cell is demonstrated by a 256-Kb SRAM macro in UMC 40-nm low-power CMOS technology. Measured full functionality is error-free from 1.1V down to 0.5V. The measured maximum operation frequency is 620MHz at 1.1V and 25℃.