| Summary: | 碩士 === 國立交通大學 === 電機工程學系 === 102 === In recent years, rapid growth of the semiconductor technology and electronic devices continuously enriches our daily life. Conventional single-function products gradually fade out from the market because those cannot satisfy the consumers’ expectations anymore. Especially for the portable devices such as smart phones and tablet PCs, power management integrated circuits (PMICs) become an essential block to deal with the various requirements from different circuits on silicon chips. This thesis focuses on digital low dropout regulator designs. Low-power, high power supply rejection (PSR), and capable of working under low-voltage environment power management module can be achieved through deliberated circuit designs.
In general, most of analog low dropout regulators rely on the negative feedback mechanism to stabilize the output voltage. To make analog circuit working properly, the input voltage needs a relative high level. Taking the CMOS technologies as an example, when the input voltage falls below one volt, several stacking architectures like cascode stages are no longer useful. Biasing scheme becomes extremely difficult and therefore it increases the design effort. Besides, with the progress of the logic/mix-mode technologies, the ratio of transistor threshold voltage to nominal supply gradually increases. The supply voltage is also decreased to prevent the device from being damaged in deep sub-micron and nano-scale technologies. This trend forces us to consider the impact of the process evolution during the design jobs.
This thesis proposes a resistance-locked loop embedded digital low dropout regulator to improve the PSR in advanced CMOS technologies. The bidirectional asynchronous wave pipeline architecture doesn’t need the external clock reference and thus the quiescent current can be minimized in steady-state. Moreover, the controller can work under a very lower input voltage. The ratio of the output voltage to input supply can be improved to avoid unnecessary loss. As for the resistance locked loop, it helps the output node free from noise generated by the switching regulator, providing a high quality output for the loading. The test chip was fabricated in UMC 40nm low-power CMOS process. Experimental results show a 77% noise suppression. The minimum supply voltage can be down to 0.6V and a 0.4 V regulated output can be guaranteed.
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