A 14-bit High Accuracy Current-Steering DAC

• Main Authors: Yu-long Sun, 孫玉龍
• Other Authors: Shao-Yun Fang
• Format: Others
• Language: zh-TW
• Published: 2014
• Online Access: http://ndltd.ncl.edu.tw/handle/95263781938376185817

碩士 === 國立臺灣科技大學 === 電子工程系 === 102 === A general methodology to construct highly matched layout pattern for multiple-device is proposed in this thesis. With these general methodologies, engineers will have more degrees of freedom for choosing layout pattern according to their innovations and the degree of circuit precision. This thesis Design a 14-bit high accuracy current-steering DAC to implement proposed layout pattern. The DAC presented is segmented architecture. The eight most significant bits are decoded from binary to thermometer code in the thermometer decoder, which steers the unary weighted current source array. The Systematic mismatch of this current source array is canceled by highly matched layout pattern. The size of transistor is decided though Monte Carlo simulation , and the layout of current source array made by Layout automation. The six bit least significant bits are implemented by a current divided circuit proposed by this thesis to enhance accuracy and update rate. The DAC would be integrated in TSMC 0.18um Mixed-Signal 1P6M process, running from 2.7V power supply. The integral nonlinearity of post-simulation is 0.034LSB, update rate is 200 MHz and the chip core area is 6.62mm2.