State Retention for Power-Gated Design with Non-uniform Multi-Bit Retention Registers
碩士 === 國立中正大學 === 電機工程研究所 === 103 === Applying retention registers to power-gated design has been one of the most effective and efficient approaches to keep the flip-flop states of idle circuit blocks during the sleep mode. Instead of applying single-bit retention registers, recent studies have show...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/w34e32 |