Design of a 10-Bit 100MS/s Pipeline Analog to Digital Converter
碩士 === 中原大學 === 電子工程研究所 === 103 === This paper design a low power 10-bit 100MS/s pipeline analog to digital converter(ADC), there are total 9 levels in this circuit, the resolution of each level is 1.5-Bit, and the last level is 2-Bit. By using operational amplifier(OP) sharing technique, two levels...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/99659604806444701549 |