ESD Protection Design in 28nm High-K / Metal Gate Process
碩士 === 國立交通大學 === 電子工程學系 電子研究所 === 103 === With the on-going shrinking of CMOS technologies, the devices in the integrated circuits (ICs) have been fabricated with ultra-thin gate oxide thickness to attain high speed and low power consumption. However, electrostatic discharge (ESD) events were not s...
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| Format: | Others |
| Language: | en_US |
| Published: |
2014
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| Online Access: | http://ndltd.ncl.edu.tw/handle/98588467377714995154 |