VerilogA-assisted Delta Sigma Modulator design
碩士 === 國立高雄海洋科技大學 === 微電子工程研究所 === 103 === As transistor numbers increases in a mixed-mode delta sigma modulator design, the HSPICE simulation time would also grows. In a typical first-order circuit-based Modulator with high oversample rate, the simulation time might take several hours. In order t...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2015
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| Online Access: | http://ndltd.ncl.edu.tw/handle/15232333003441053572 |