| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 103 === Asynchronous circuits, which require not global clock signal, may have the advantages of lower power consumption, better tolerance to device variations, better circuit modularity and easier reuse. Thus, asynchronous circuit has been revisited by many research groups for the adoption in circuit design with advanced semiconductor technologies. Since no synchronization is needed, data are processed as they become available; when the results are available they are fed to the next stage as soon as possible. As a result, the asynchronous circuit can achieve average-delay performance, in order to further optimize asynchronous circuits performance, the average delay needs to be calculated efficiently. It is the ultimate goal of this research to find an effective way for asynchronous circuit optimization.
As the first step, this thesis studies and proposes ways to find the average-case delay which is given digital combination circuit blocks. The event-driven approach can simulate the digital circuit accurately and thus produce the average delay reliably. However, as the number of gates increases, the simulation time can be extensive. Using probabilistic signal propagation, it is possible to calculate the average delay systematically. However, when there are reconvergent fanout paths in the circuit, this probabilistic approach becomes quite complicated, and may produce inaccurate results or take a long time for detailed simulations. This thesis proposes to group the gates around the reconvergence paths to form supergates, and create necessary circuit modules for these supergates such that they can be simulated in the same way as a primitive gate. Thus, significant saving in simulation time and more accurate average delay time can be obtained.
To be compatible to the existing commercial tools, circuit description in Standard Delay Format (SDF) is processed and a reliable event-driven simulator has been implemented. Using this event-driven simulator with the supergate capability, the next step of asynchronous circuit optimization may be carried out in the near future.
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