| Summary: | 碩士 === 國立臺北科技大學 === 電機工程研究所 === 103 === With the development of modern science and technology, the number of modules within the integrated circuit is also growing rapidly, but the classical floorplanning algorithm is difficult to maintain satisfactory results of massive modules. Therefore, this paper presents a new floorplanning method for a large number of modules. In addition to considering the floorplan size, wire length, the power distribution balance and time is also considerations.
This paper presents a multi-stage approach to achieve the requirements listed above. First Polish expression of the module structure combine into large modules, then use Simulated Annealing algorithm to be floorplan, finally modules to be exchange to achieve optimized wire length. The whole process, in addition to considering the floorplan size and the wire length, also taking into account the distribution of the balance of power, in order to prevent a decrease in the area, the power generated by the imbalance in the distribution problem. The results of this study show that can reduce design complexity and reach a good floorplan, and get better power density distribution and the wire length.
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