| Summary: | 碩士 === 國立中央大學 === 電機工程學系 === 104 === Content addressable memory (CAM) plays an important role in many digital systems. For supporting the function of parallel search, a CAM cell is composed of a storage element and a comparator. This causes that the testing of CAM is more difficult than that of RAM. More and more large-capacity CAMs are needed for network-related applications. Effective yield-enhancement techniques are imperative for these large embedded or stand-alone CAMs.
Built-in self-repair (BISR) technique is one effective method for enhancing the yield of embedded memories. One main challenge of CAM BISR is that the fault location capability of the used test algorithms. A test algorithm for CAMs must have compare test operations for observing the test responses. Once a compare operation detects a fault, however, we only can know the faulty row/column and cannot know the location of faulty cell. In this thesis, we propose a BISR scheme with fault diagnosis capability for CAMs. A fault-location algorithm is proposed to identify the location of faulty cell in a CAM with priority address encoder. The BISR uses the fault-location algorithm to identify the location of faulty cells such that the repair efficiency is boosted. To evaluate the repair efficiency of the proposed BISR scheme, furthermore, an evaluation tool for estimating the repair rate of the BISR scheme is proposed. Simulation results show that the BISR with the fault diagnosis capability can
provide much better repair rate in comparison with the BISR without the fault diagnosis capability. The area overhead of the BISR circuit is about 3.29% for a 512x128-bit CAM using TSMC 0.13um CMOS standard cell library.
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