晶片測試載板高速訊號佈局分析
碩士 === 國立高雄第一科技大學 === 電子工程系碩士在職專班 === 104 === This paper focuses on the Final Test/FT stage of the current IC design industry. IC tested Load Board is a transmitted interface board between IC and Automatic Test Equipment (ATE). The layout of high-speed signals are analyzed to ensure that the signal...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/47039614909603196257 |