| Summary: | 碩士 === 國立清華大學 === 電機工程學系 === 104 === In recent years, lager data storages and higher speed data transfer interfaces have been widely used. As the chip operation speed increasing, the larger electronic-magnetic interference (EMI) will be produced. To restrain the EMI becomes a major issue in high speed application. There are two ways to suppress the EMI: one is to add shielding on the outside of the chip; the other is to use the spread spectrum clocking (SSC) inside the chip. The former is costly and inefficient, the latter can reduce the EMI from its source, so it’s an effective and popular method. The communication systems contain high speed serial link, such as Serial Advanced Technology Attachment (SATA)
This work presents SSCG for SATA3.0. The SSCG utilizes phase switching at the low speed part of the divider to achieve point 5 divider resolution. The phase switching circuit will be added at the end of the integer divider chain. Hence the quantization noise can be repressed and decreasing the power consumption. The switching circuit just contains two resample D flip-flops, a multiplexer to select the final output of the divider and a control logic to manipulate the point 5 divider ratio mechanism.
This chip is fabricated in TSMC 1P6M 0.18um. The output frequency range is from 5.97G to 6G Hz, and the EMI reduction is 14dB with 4883 ppm spreading ratio. The power consumption is 38mW under 1.8V supply voltage. The chip area is 1090×1330µm^2.
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