| Summary: | 碩士 === 國立虎尾科技大學 === 電子工程系碩士班 === 104 === In this thesis, two low temperature-coefficient CMOS reference voltage circuits have been proposed. The design principle is based on using the characteristics of the forward-biased pn junction of the BJT transistor to generate the necessary positive and negative temperature-coefficients. Appropriately combine the positive and negative temperature-coefficients, a zero temperature coefficient reference voltage circuit can be realized. Besides, second order temperature-coefficient compensation has been performed to further reduce the variation of the output voltages. As compared with the existed reference voltage circuits, the proposed circuit benefits from low-power consumption, simpler circuit architecture, and less chip area. In this thesis, detailed design principle has been disclosed, also the HSPICE and LAKER simulation program with 0.35-m process parameters have been used to perform the pre-layout and post-layout simulations. According to the post-layout simulation results, under the supply voltage of 2.4V, as the temperature varies from -20oC to 120oC, the output voltage variations of the proposed second order single-ended reference voltage is 0.052mV, the corresponding power dissipation is only 0.457mW and the variation per temperature is 3.04 ppm/˚C. The simulation results of the proposed second order differential mode reference voltage circuit shows that, under the supply voltage of 2.4V, the temperature varies from -20oC to 120oC, the output voltage changes 8.603mV, the power dissipation is only 0.897mW and the variation per temperature is 132.31ppm/˚C. Both the simulation results are consistent with the theoretic analysis. The proposed circuit can be applied to different analog circuits.
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