3D IC Memory BIST Design and Test Scheduling under Power Constraints
碩士 === 中原大學 === 電子工程研究所 === 105 === With the increasing number of embedded memory cores in modern electronic system designs, the cost of memory testing becomes significant. Built-in-self-test (BIST) is an effective approach for memory testing. However, memory BIST for three-dimensional integrated ci...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/71021599394150571984 |