| Summary: | 碩士 === 國立交通大學 === 電子研究所 === 105 === IFO memory is commonly used for data buffers and flow control in many SoC applications. Simultaneously, extended battery lifetime is needed. Therefore, an ultra-low power FIFO memory becomes a significant design concern. Besides, to reduce memory area in chip, compared to conventional design that each user has its own FIFO memory, in this thesis, a novel multi-user FIFO memory and optimized memory allocation algorithm are proposed to reduce power consumption. Secondly, a two port disturbance-free 12T near-/sub-threshold SRAM bit-cell with cross-point data-aware Write word-line structure is illustrated. The 12T cell eliminates not only read disturbance but also write half-select disturbance for robust sub-threshold operation. An adaptive read operation timing tracing circuit and negative bit-line circuit are employed in the design for PVT variation-tolerant read operation and write ability enhancement. Thirdly, the proposed ripple bit-line structure divide the bit-line into several segments. Therefore, the wire delay can be reduced apparently. Fourthly, to reduce area overhead of the link table used for memory address allocation, in this thesis, we set continuous sixteen pieces of data as an unit. Therefore, the self-timed pointers are proposed to save a long metal line and a clock signal, which further save the power consumption about 59% comparing to shift-register-based pointers. Fifthly, the link table is verified by Verilog. Finally, a 4kb ultra-low power FIFO memory in UMC 28nm HKMG technology with the proposed 12T two port SRAM bit-cell is implemented. It can execute two write or two read operation simultaneously. Under the condition with the same or better SNM comparing to previous FIFO memories, this design has double throughput which is suitable for bio-sensing and IoT platforms.
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