Rethinking Last-level-cache Write-back Strategy for MLC STT-MRAM Main Memory with Asymmetric Write Energy
碩士 === 國立清華大學 === 資訊工程學系所 === 105 === To meet the requirement of low-power consumption, multi-level-cell STT-RAM (MLC STT-RAM) has been widely regarded as a potential candidate for replacing DRAM-based main memory in the next generation computer architectures because of its high cell density, compar...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2017
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| Online Access: | http://ndltd.ncl.edu.tw/handle/rq6ssd |