10-Bit 1GS/s Binary-Weighted Current-Steering D/A Converter
碩士 === 國立臺灣科技大學 === 電子工程系 === 105 === A 10-bit 1GS/s digital-to-analog converter designed in a TSMC 90 nm 1P9M CMOS technology with binary-weighted current-steering architecture to achieve high operation speed and high accuracy is proposed in this thesis. According to the limitation of low supply vo...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2016
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| Online Access: | http://ndltd.ncl.edu.tw/handle/37113762933858746716 |
| Summary: | 碩士 === 國立臺灣科技大學 === 電子工程系 === 105 === A 10-bit 1GS/s digital-to-analog converter designed in a TSMC 90 nm 1P9M CMOS technology with binary-weighted current-steering architecture to achieve high operation speed and high accuracy is proposed in this thesis. According to the limitation of low supply voltage and short-channel effect, it is difficult to design an accurate enough current source array. Therefore, a current-splitter architecture along with the 2nd order gradient cancellation layout is adopted to ensure the required accuracy.
The integral nonlinearity (INL) and differential nonlinearity (DNL) are simulated to be ±0.12 LSB and +0.17~-0.14 LSB respectively. With 499.76MHz input sinewave, the spurios free dynamic range (SFDR) is 51 dB. The power consumption is 24 mW and the active area is merely 0.25 (mm)^2.
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