10-Bit 1GS/s Binary-Weighted Current-Steering D/A Converter
碩士 === 國立臺灣科技大學 === 電子工程系 === 105 === A 10-bit 1GS/s digital-to-analog converter designed in a TSMC 90 nm 1P9M CMOS technology with binary-weighted current-steering architecture to achieve high operation speed and high accuracy is proposed in this thesis. According to the limitation of low supply vo...
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ndltd-TW-105NTUS54280132017-03-31T04:39:19Z http://ndltd.ncl.edu.tw/handle/37113762933858746716 10-Bit 1GS/s Binary-Weighted Current-Steering D/A Converter 十位元1GS/s之二進位電流式數位類比轉換器 Yuan-Yuan - Hsiao 蕭媛元 碩士 國立臺灣科技大學 電子工程系 105 A 10-bit 1GS/s digital-to-analog converter designed in a TSMC 90 nm 1P9M CMOS technology with binary-weighted current-steering architecture to achieve high operation speed and high accuracy is proposed in this thesis. According to the limitation of low supply voltage and short-channel effect, it is difficult to design an accurate enough current source array. Therefore, a current-splitter architecture along with the 2nd order gradient cancellation layout is adopted to ensure the required accuracy. The integral nonlinearity (INL) and differential nonlinearity (DNL) are simulated to be ±0.12 LSB and +0.17~-0.14 LSB respectively. With 499.76MHz input sinewave, the spurios free dynamic range (SFDR) is 51 dB. The power consumption is 24 mW and the active area is merely 0.25 (mm)^2. Poki Chen 陳伯奇 2016 學位論文 ; thesis 85 zh-TW |
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碩士 === 國立臺灣科技大學 === 電子工程系 === 105 === A 10-bit 1GS/s digital-to-analog converter designed in a TSMC 90 nm 1P9M CMOS technology with binary-weighted current-steering architecture to achieve high operation speed and high accuracy is proposed in this thesis. According to the limitation of low supply voltage and short-channel effect, it is difficult to design an accurate enough current source array. Therefore, a current-splitter architecture along with the 2nd order gradient cancellation layout is adopted to ensure the required accuracy.
The integral nonlinearity (INL) and differential nonlinearity (DNL) are simulated to be ±0.12 LSB and +0.17~-0.14 LSB respectively. With 499.76MHz input sinewave, the spurios free dynamic range (SFDR) is 51 dB. The power consumption is 24 mW and the active area is merely 0.25 (mm)^2.
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author2 |
Poki Chen |
author_facet |
Poki Chen Yuan-Yuan - Hsiao 蕭媛元 |
author |
Yuan-Yuan - Hsiao 蕭媛元 |
spellingShingle |
Yuan-Yuan - Hsiao 蕭媛元 10-Bit 1GS/s Binary-Weighted Current-Steering D/A Converter |
author_sort |
Yuan-Yuan - Hsiao |
title |
10-Bit 1GS/s Binary-Weighted Current-Steering D/A Converter |
title_short |
10-Bit 1GS/s Binary-Weighted Current-Steering D/A Converter |
title_full |
10-Bit 1GS/s Binary-Weighted Current-Steering D/A Converter |
title_fullStr |
10-Bit 1GS/s Binary-Weighted Current-Steering D/A Converter |
title_full_unstemmed |
10-Bit 1GS/s Binary-Weighted Current-Steering D/A Converter |
title_sort |
10-bit 1gs/s binary-weighted current-steering d/a converter |
publishDate |
2016 |
url |
http://ndltd.ncl.edu.tw/handle/37113762933858746716 |
work_keys_str_mv |
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