| Summary: | 碩士 === 國立臺北科技大學 === 電子工程系碩士班（碩士在職專班） === 105 === “Last Mile” policy is one of the internet architects promoted by government for
Digital Subscriber Line; DSL, with decades efforts ADSL (Asymmetric Digital
Subscriber Line) had developed to VDSL (Vey High Digital Subscriber Line) and to the
super high speed, G.FAST technology, the technology using vectoring to propel the
transmission speed up to 1Gbps.
During the development of the system design, the noise and signal disturbance are the
biggest challenges to face for an engineer. The power design plays the decisive role to
credit the project. To design a power tree and circuits in order to provide a steady power
current is a must for a good design. The difficulty such as control the ripples when
in-rush currents happen, since the power tree is consist of many DC-DC converters, to
smooth out the ripples is very critical. As well as the circuit to make sure the power
runs the shortest path and minimize the noise created by flowing current In the report, I
would like to elaborate the technique when main power entering the power floor map
and switching layers at the first time and compare it to the reference design.At the end,
the report will also discuss how the E-cap (electrolytic capacitor) influences ripple
voltage and company with few experiments to justify some assumptions.I also would like to show the comparison data of Broadcom reference design with a retailed product over transmission speed, In the 100 meters is also more 2.3%, 250 meters, also has 12% of the progress, in 500 meters, also more 36.5% progress.
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