Power Optimization for Activity-Driven Clock Trees
碩士 === 中原大學 === 電子工程研究所 === 106 === In recent years, with the progress of technology, the method to reduce power consumption and circuit area has become a very important issue. In a synchronous sequential circuit, clock gating is recognized as a useful technique to reduce power consumption. Conventi...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | zh-TW |
| Published: |
2018
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| Online Access: | http://ndltd.ncl.edu.tw/handle/tkkk3g |