High-Efficiency Test Compression Technology and On-Chip Self-Test Methodology with All Deterministic Compressed Test Patterns Recorded in Low Power Scan Chains

High-Efficiency Test Compression Technology and On-Chip Self-Test Methodology with All Deterministic Compressed Test Patterns Recorded in Low Power Scan Chains

碩士 === 國立成功大學 === 電腦與通信工程研究所 === 106

Bibliographic Details
Main Authors: Bo-RenChen, 陳柏任
Other Authors: Kuen-Jong Lee
Format: Others
Language:en_US
Published: 2018
Online Access:http://ndltd.ncl.edu.tw/handle/tnk8rp
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spelling ndltd-TW-106NCKU56520042019-05-16T00:30:06Z http://ndltd.ncl.edu.tw/handle/tnk8rp High-Efficiency Test Compression Technology and On-Chip Self-Test Methodology with All Deterministic Compressed Test Patterns Recorded in Low Power Scan Chains 高壓縮測試資料技術及將所有壓縮測試向量儲存於低功耗掃描鏈之晶片內自我測試架構 Bo-RenChen 陳柏任 碩士 國立成功大學 電腦與通信工程研究所 106 Kuen-Jong Lee 李昆忠 2018 學位論文 ; thesis 56 en_US
collection NDLTD
language en_US
format Others
sources NDLTD
description 碩士 === 國立成功大學 === 電腦與通信工程研究所 === 106
author2 Kuen-Jong Lee
author_facet Kuen-Jong Lee
Bo-RenChen
陳柏任
author Bo-RenChen
陳柏任
spellingShingle Bo-RenChen
陳柏任
High-Efficiency Test Compression Technology and On-Chip Self-Test Methodology with All Deterministic Compressed Test Patterns Recorded in Low Power Scan Chains
author_sort Bo-RenChen
title High-Efficiency Test Compression Technology and On-Chip Self-Test Methodology with All Deterministic Compressed Test Patterns Recorded in Low Power Scan Chains
title_short High-Efficiency Test Compression Technology and On-Chip Self-Test Methodology with All Deterministic Compressed Test Patterns Recorded in Low Power Scan Chains
title_full High-Efficiency Test Compression Technology and On-Chip Self-Test Methodology with All Deterministic Compressed Test Patterns Recorded in Low Power Scan Chains
title_fullStr High-Efficiency Test Compression Technology and On-Chip Self-Test Methodology with All Deterministic Compressed Test Patterns Recorded in Low Power Scan Chains
title_full_unstemmed High-Efficiency Test Compression Technology and On-Chip Self-Test Methodology with All Deterministic Compressed Test Patterns Recorded in Low Power Scan Chains
title_sort high-efficiency test compression technology and on-chip self-test methodology with all deterministic compressed test patterns recorded in low power scan chains
publishDate 2018
url http://ndltd.ncl.edu.tw/handle/tnk8rp
work_keys_str_mv AT borenchen highefficiencytestcompressiontechnologyandonchipselftestmethodologywithalldeterministiccompressedtestpatternsrecordedinlowpowerscanchains
AT chénbǎirèn highefficiencytestcompressiontechnologyandonchipselftestmethodologywithalldeterministiccompressedtestpatternsrecordedinlowpowerscanchains
AT borenchen gāoyāsuōcèshìzīliàojìshùjíjiāngsuǒyǒuyāsuōcèshìxiàngliàngchǔcúnyúdīgōnghàosǎomiáoliànzhījīngpiànnèizìwǒcèshìjiàgòu
AT chénbǎirèn gāoyāsuōcèshìzīliàojìshùjíjiāngsuǒyǒuyāsuōcèshìxiàngliàngchǔcúnyúdīgōnghàosǎomiáoliànzhījīngpiànnèizìwǒcèshìjiàgòu
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