Timing-driven layer assignment

• Main Authors: Guan-Hua Huang, 黃冠華
• Other Authors: Yih-Lang Li
• Format: Others
• Language: zh-TW
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/7vbvfc

碩士 === 國立交通大學 === 資訊科學與工程研究所 === 106 === As the development of very-large-scale integration (VLSI) circuit continues to advance, the feature size scales down to nanometer-level. The width of a metal wire used in a circuit also decreases, which increases the metal resistance and thus the interconnect delay. Therefore timing-driven layer assignment is essential to high-performance design, which considers the delay and via number optimization at the same time during layer assignment. This thesis describes a layer assignment algorithm, which sets different cost functions for timing-critical nets and non-timing-critical nets. For the timing-critical nets, timing-relevant parameters are first considered to get better interconnect delay; on the other hand, for the non-timing-critical nets, the via usage is minimzed as the traditional method does. In the experiments, we evaluate the results by Elmore delay model, and compute the delay improvement rate between the traditional method and the algorithm proposed in this thesis.