Layout-Based Methodology of Dual-Cell-Aware Tests

• Main Authors: Wu, Tse-Wei, 吳則緯
• Other Authors: Chao, Chia-Tso
• Format: Others
• Language: en_US
• Published: 2017
• Online Access: http://ndltd.ncl.edu.tw/handle/8tc6s7

碩士 === 國立交通大學 === 電子研究所 === 106 === This thesis proposed a new DCA fault model generate flow to improve the performance of our previous work. We achieve this by changing our method to extract defect in a dual-cell. In this work we do not need to run RC-extraction for every dual-cell pair through the commercial tools anymore, we parsing the cell layout information and find the potential defect to instead. On the other hand, we also proposed a method to delete some defect seems impossibly to happen so we could reduce our simulation time and fault volume. Finally, we generate pattern by commercial ATPG tools to compare our results.