Design of Divide-by-2 and 6 Injection-Locked Frequency Dividers Using LC Resonator

• Main Authors: Chung–Yi Huang, 黃崇溢
• Other Authors: Sheng–Lyang Jang
• Format: Others
• Language: zh-TW
• Published: 2018
• Online Access: http://ndltd.ncl.edu.tw/handle/8d73b6

碩士 === 國立臺灣科技大學 === 電子工程系 === 106 === In the RF transceiver, PLL is very important, PLL components include Phase Frequency Detector, Charge Pump, Loop Filter, Voltage Controlled Oscillator (VCO), and Frequency Divider. The most important characteristics of divider performance are low-power, low phase noise, wide locking range. This thesis presents the design of Injection-Locked Frequency Dividers (ILFDs). Firstly, a single-stage ÷6 LC ILFD designed in the TSMC 0.18 μm CMOS process. Conventional harmonic mixer divide-by-6 ILFD and other ILFDs using two-step mixing approach have limited locking range, and this chapter shows a wide locking range divide-by-6 ILFD designed with linear mixer technique. At the drain-source bias VDD of 1 V and at the incident power of 0 dBm, the locking range is 2.3 GHz, from the incident frequency 11.3 GHz to 13.6 GHz. The free-running oscillation frequency is 1.9 GHz. The core power consumption is 9.52 mW and the die area is 0.862 × 1.148 mm2. Secondly, measurement of locking range property at high injection power is applied to a CMOS LC-tank ILFD with dual-resonance LC resonator. The LC ILFD has two oscillation frequency bands at 3.2 GHz and 1.9 GHz while tuning the varactor control voltage. The divide-by-2 ILFD at 0 dBm input power has two non-overlapped locking ranges from 2.0 GHz to 3.5 GHz and from 5.1 GHz to 9.2 GHz. At low injection power, the ILFD has two non-overlapped locking ranges categorized as low-band and high-band locking ranges. At high injection power, the low-band locking range is split to two sub-low-frequency band locking ranges. This finding is attributed to the distributed resonator because of parasitic capacitance along the metal traces. Thirdly, conventional LC ILFDs often have one locking range at 0 dBm injection power, and it takes for granted that these ILFDs use a resonator with one resonant frequency. This chapter presents measured locking ranges of a CMOS divide-by-2 ILFD with coupled inductors as the LC resonator. The studied ILFD is subject to input power between -20 dBm to 10 dBm. It is found the divide-by-2 ILFD at 0 dBm input power has one single-band locking range and has two non-overlapped locking ranges at injection power equal to 10 dBm. This fact shows overlapping of locking ranges has been used without special notification. Fourthly, this chapter studies the locking range of a CMOS divide-by-2 ILFD previously designed for using overlapped locking range to emulate a wide single-band locking range. The ILFD uses two symmetric spiral inductors and one center-tapped spiral inductor and a pair of varactors to build a dual-resonance RLC resonator, with which the ILFD has two overlapped or non-overlapped locking ranges. The ILFD also has three non-overlapped locking ranges, this indicates the ILFD uses a distributed spiral resonator, and the ILFD uses triple-resonance resonator. The chip uses an area is 0.758 × 0.822 mm2. And finally, this chapter measures the locking range of a CMOS divide-by-2 ILFD using two direct injection MOSFETs. The fabricated 0.18 μm CMOS ÷2 ILFD uses direct cross-coupled switching transistors and a dual-resonance resonator. Two injection methods: balanced and unbalanced configurations are applied to analyze the circuit performance. In the balanced case, the ILFD has a single-band like locking range. In the unbalanced, three locking ranges can be identified. The consumed power of the ÷2 ILFD core is 10 mW at the dc drain-source voltage 0.8 V. At an external injected signal power Pinj = 0 dBm, the measured locking range is 5.7 GHz from 4.0 to 9.7 GHz.