| Summary: | 碩士 === 國立交通大學 === 資訊科學與工程研究所 === 107 === Due to the recent escalation in the cost and complexity of the integrated circuits (ICs) design process, using third-party resources in modern ICs design has become a trend; thus, ICs design has been more prone to various kinds of attacks in the supply chain. Hardware Trojan horses (HTHs) can be implanted to facilitate the leakage of confidential information to adversaries or destroy the IC system under a specific condition. In addition, one of the main categories of HTHs is to tamper with IC reliability and accelerate the aging of the chip, which is called reliability Trojan.
The aim of this research is to develop a post-layout staged reliability Trojan that controls the lifetime of a power delivery network (PDN) by manipulating electromigration-induced aging. In addition to attack, this Trojan could be utilized by designers to strengthen the robustness of PDN. In this work, we transformed our Trojan problem into a min-cut problem and further considered process variation (PV), an uncertainty as regards to HTHs effectiveness, to efficiently control system lifetime under PV. Experiments based on 28 nm designs demonstrated that our proposed methodology could control the system lifetime with only 4.3\% average error rate under PV.
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