Design and Implementation of Dual-Antenna GPSR using SoC FPGA Platform
碩士 === 國立交通大學 === 機械工程系所 === 107 === When using the Global Positioning System (GPS), the receiver needs to receive the satellite signals continuously for more than six seconds to ensure the success of signal decoding and positioning. In a flight scenario that the aircraft is rotating, the satellite-...
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ndltd-TW-107NCTU54890322019-05-16T01:40:47Z http://ndltd.ncl.edu.tw/handle/89gk7t Design and Implementation of Dual-Antenna GPSR using SoC FPGA Platform 雙天線GPS接收器於SoC FPGA上的設計與實現 Li, Ting-Yu 李定宇 碩士 國立交通大學 機械工程系所 107 When using the Global Positioning System (GPS), the receiver needs to receive the satellite signals continuously for more than six seconds to ensure the success of signal decoding and positioning. In a flight scenario that the aircraft is rotating, the satellite-signal-receiving-path would be interfered by the body of the aircraft, which leads to the failure of positioning task. To solve this problem, we proposed using two antennas, located on the opposite sides of the aircraft, to ensure that at least one antenna can receive the satellite signal. There are several methods in literatures regarding the two-antenna approach. For example, one uses radio frequency (RF) combiner to lump signals from two antennas together; one uses RF switch to take satellite signal from one antenna at a time; one uses two RF frontend and two baseband processors to process the satellite signal from two antennas, independently. Although there are pros and cons in above approaches, one thing in common is that, after receiving the raw data from RF frontends, they all process the signal like conventional method of one-antenna system. In this thesis, we proposed a novel architecture using two RF frontends and one baseband processor. By modifying the conventional algorithm, one can successfully conduct the positioning task using the intermittent signals from each antenna. In this project, we uses FPGA SoC platform to implement the GPS receiver, instead of the conventional approach which uses an ASIC baseband processor and a microcontroller. Due to the compact design of the FPGA SoC, the realization of the signal processing algorithm is flexible, the power consumption is low, and the circuit board is downsized. The experimental results indicated that the proposed method can successfully complete the positioning task when the satellite signals are switched between two RF frontend at the frequency of 4Hz and the duty ratio of 75%. Chen, Tsung-Lin 陳宗麟 2018 學位論文 ; thesis 64 zh-TW |
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碩士 === 國立交通大學 === 機械工程系所 === 107 === When using the Global Positioning System (GPS), the receiver needs to receive the satellite signals continuously for more than six seconds to ensure the success of signal decoding and positioning. In a flight scenario that the aircraft is rotating, the satellite-signal-receiving-path would be interfered by the body of the aircraft, which leads to the failure of positioning task. To solve this problem, we proposed using two antennas, located on the opposite sides of the aircraft, to ensure that at least one antenna can receive the satellite signal.
There are several methods in literatures regarding the two-antenna approach. For example, one uses radio frequency (RF) combiner to lump signals from two antennas together; one uses RF switch to take satellite signal from one antenna at a time; one uses two RF frontend and two baseband processors to process the satellite signal from two antennas, independently. Although there are pros and cons in above approaches, one thing in common is that, after receiving the raw data from RF frontends, they all process the signal like conventional method of one-antenna system. In this thesis, we proposed a novel architecture using two RF frontends and one baseband processor. By modifying the conventional algorithm, one can successfully conduct the positioning task using the intermittent signals from each antenna.
In this project, we uses FPGA SoC platform to implement the GPS receiver, instead of the conventional approach which uses an ASIC baseband processor and a microcontroller. Due to the compact design of the FPGA SoC, the realization of the signal processing algorithm is flexible, the power consumption is low, and the circuit board is downsized. The experimental results indicated that the proposed method can successfully complete the positioning task when the satellite signals are switched between two RF frontend at the frequency of 4Hz and the duty ratio of 75%.
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Chen, Tsung-Lin |
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Chen, Tsung-Lin Li, Ting-Yu 李定宇 |
author |
Li, Ting-Yu 李定宇 |
spellingShingle |
Li, Ting-Yu 李定宇 Design and Implementation of Dual-Antenna GPSR using SoC FPGA Platform |
author_sort |
Li, Ting-Yu |
title |
Design and Implementation of Dual-Antenna GPSR using SoC FPGA Platform |
title_short |
Design and Implementation of Dual-Antenna GPSR using SoC FPGA Platform |
title_full |
Design and Implementation of Dual-Antenna GPSR using SoC FPGA Platform |
title_fullStr |
Design and Implementation of Dual-Antenna GPSR using SoC FPGA Platform |
title_full_unstemmed |
Design and Implementation of Dual-Antenna GPSR using SoC FPGA Platform |
title_sort |
design and implementation of dual-antenna gpsr using soc fpga platform |
publishDate |
2018 |
url |
http://ndltd.ncl.edu.tw/handle/89gk7t |
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