A Clock and Data Recovery Circuit with Quarter-Rate Linear Phase Detector
碩士 === 國立彰化師範大學 === 電子工程學系 === 107 === With the evolution and scaling down of CMOS technology, the computing performance of a single chip has exponentially increasing. Accordingly, the improvement of I/O bandwidth is indispensable. High-speed serial data links provide multi-gigabit bandwidth with re...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2019
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| Online Access: | http://ndltd.ncl.edu.tw/handle/kr396v |