Detecting Critical Timing Paths Caused by Dynamic Voltage Drop Using Machine Learning
碩士 === 國立臺灣大學 === 資訊工程學研究所 === 107 === Timing constrain will reduce operational frequency of large integrated circuits or system-on-a-chip, and it is often caused by setup timing violation which would be influenced by dynamic voltage drop, can be referred to as maximum timing pushout. This problem i...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2019
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| Online Access: | http://ndltd.ncl.edu.tw/handle/j9nhr6 |