Divide-by-4 , Divide-by 7 and Divide-by 10 Injectio-Locked Frequency Dividers

• Main Authors: Po-Ming Shih, 石博名
• Other Authors: Sheng-Lyang Jang
• Format: Others
• Language: en_US
• Published: 2019
• Online Access: http://ndltd.ncl.edu.tw/handle/n3tdqg

碩士 === 國立臺灣科技大學 === 光電工程研究所 === 107 === 　　With the rapid development of wireless communication systems, various frequency synthesizers have been developed, with system-on-chip as the main trend. Among them, Phase-Locked-Loop (PLL) has a wide range of applications in many fields, such as wireless communication, digital TV, and broadcasting. In wireless communication systems, the characteristics of the PLL are very important, including the phase detector (PFD), charging pump (CP), loop filter (LF), voltage controlled oscillator (VCO), and frequency divider ( FD), the above-mentioned voltage-controlled oscillator and frequency divider are the core circuits, and this paper mainly studies three different injection-locked frequency divider designs. 　　First, we study a CMOS divide-by-4 injection-locked frequency divider (ILFD) with a divide-by-2 ring oscillator stacked on a capacitive cross-coupled oscillator used as an LC divide-by-2 ILFD. The divide-by-4 ILFD in the TSMC 0.18 μm 3P6M BiCMOS process has a locking range from 6.1 GHz to 10.9 GHz at the power consumption of 8.24 mW. The varactor-less divide-by-4 ILFD and occupies a small area of 0.939×0.7284 mm2. 　　Secondly, a wide locking range divide-by-7 LC ILFD manufactured in the TSMC 0.18 μm processes. The 7:1 LC ILFD uses three spiral inductors and parasitic capacitors as the resonator, a capacitive cross-coupled switching FETs and two injection FETs in series with two inductors. The die area is 1.084 ×1.042 mm2. The proto-type 0.18 μm CMOS ILFD has the locking range 2.2 GHz from 15.7 GHz to 17.9 GHz at the power consumption of 9 mW. 　　Finally, a CMOS divide-by-10 injection-locked frequency divider (ILFD) with a divide-by-2 current-mode logic (CML) stacked on a capacitive cross-coupled oscillator used as an LC divide-by-5 ILFD. the divide-by-10 ILFD in the TSMC 0.18 μm 1P6M CMOS process has a locking range 1.25 GHz from 15.0 GHz to 16.25 GHz at the power consumption of 12.5 mW. The divide-by-10 ILFD uses the CML FD with wide locking range to track the input frequency from the LC ILFD output, and occupies a small area of 1.2×1.2 mm2. The ILFD can be used in divide-by-6 mode.