System Interconnection Design Trade-offs in Three-Dimensional (3-D) Integrated Circuits

System Interconnection Design Trade-offs in Three-Dimensional (3-D) Integrated Circuits

Continued technology scaling together with the integration of disparate technologies in a single chip means that device performance continues to outstrip interconnect and packaging capabilities, and hence there exist many difficult engineering challenges, most notably in power management, noise isol...

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Bibliographic Details
Main Author: Weerasekera, Roshan
Format: Doctoral Thesis
Language:English
Published: KTH, Elektronik- och datorsystem, ECS 2008
Subjects:
Interconnects
Parasitic Extraction
Repeaters
Signal Integrity
System-on-Chip (SoP)
System-in-Package (SiP)
System-on-Package (SoP)
Three-dimensional (3-D) Integration
Through-Silicon-Via (TSV)
Vertical Integration
Information technology
Informationsteknik
Online Access:http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-9586
http://nbn-resolving.de/urn:isbn:978-91-7415-169-5

Internet

http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-9586
http://nbn-resolving.de/urn:isbn:978-91-7415-169-5

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