An Energy-efficient 32-bit multiplier architecture in 90nm CMOS

An Energy-efficient 32-bit multiplier architecture in 90nm CMOS

A fast and energy-efficient multiplier is always needed in electronics industry especially DSP, image processing and arithmetic units in microprocessors. Multiplier is such an important element which contributes substantially to the total power consumption of the system. On VLSI level, the area also...

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Bibliographic Details
Main Author: Mehmood, Nasir
Format: Others
Language:English
Published: Linköpings universitet, Institutionen för systemteknik 2006
Subjects:
Modified Booth-encoding
carry save adder
multiplier
partial products
CMOS power
VLSI
SOC
Cadence
Electrical engineering
Elektroteknik
Online Access:http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7435

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http://urn.kb.se/resolve?urn=urn:nbn:se:liu:diva-7435

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