Mechanical stress and circuit aging aware VLSI CAD
With the gradual advance of the state-of-the-art VLSI manufacturing technology into the sub-45nm regime, engineering a reliable, high performance VLSI chip with economically attractive yield in accordance with Moore's law of scaling and integration has become extremely difficult. Some of the mo...
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| Format: | Others |
| Language: | English |
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2011
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| Online Access: | http://hdl.handle.net/2152/ETD-UT-2010-12-2459 |