Nanometer VLSI design-manufacturing interface for large scale integration

Nanometer VLSI design-manufacturing interface for large scale integration

As nanometer Very Large Scale Integration (VLSI) demands more transistor density to fabricate multi-cores and memory blocks in a limited die size, many researches have been performed to keep Moore's Low in two different ways: 2D geometric shrinking and 3D vertical wafer stacking. For the geomet...

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Bibliographic Details
Main Author: Yang, Jae-Seok
Format: Others
Language:English
Published: 2011
Subjects:
Double patterning
TSV
3D integration
3-D integration
Overlay
Layout decomposition
Lithography
Online Access:http://hdl.handle.net/2152/ETD-UT-2011-05-3070

Internet

http://hdl.handle.net/2152/ETD-UT-2011-05-3070

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