Design Methodologies and CAD Tools for Leakage Power Optimization in FPGAs
The scaling of the CMOS technology has precipitated an exponential increase in both subthreshold and gate leakage currents in modern VLSI designs. Consequently, the contribution of leakage power to the total chip power dissipation for CMOS designs is increasing rapidly, which is estimated to be 40%...
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| Language: | en |
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2008
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| Online Access: | http://hdl.handle.net/10012/3856 |